90008166

open access

Version of Record

3-D CMOS Chip Stacking for Security ICs Featuring Backside Buried Metal Power Delivery Networks With Distributed Capacitance

English (英語)

IEEE Transactions on Electron Devices

68(4)

2077-2082

Institute of Electrical and Electronics Engineers (IEEE)

2021-04

2021-04-21

3-D stacks of complimentary metal-oxide-semiconductor (CMOS) integrated circuit (IC) chips for security applicationsmonolithicallyembed backside buried metal (BBM) routing with low series impedance and high decoupling capability in a power delivery network (PDN), thanks to distributed capacitances over a full-chip backside area. The 3-D Si demonstrator integrating cryptographic engines was fabricated in a 0.13-mu m CMOS technology with post-Si wafer-level BBM Cu processing with 10, 15, and 10 mu m of thickness, linewidth, andspace, respectively, along with through Si vias (TSVs) with 10 and 40 mu m of diameter and depth, respectively. The capacitance of 0.18 nF/mm(2) in the effective backside area of 71 mm(2) suppressed dynamic IR drops in 10% and 59% for the single chip and four chip stack samples, respectively, during the operation of a 3.9 M-gate crypto core at 30 MHz. On-chip power noise monitoring (OCM) was applied in these measurements. The 3-D BBM PDN also effectively reduces power side channel information leakage, which is evaluated by 14x increase in the number of externally observed electromagnetic (EM) noise waveforms to attain the t- test value of larger than 4.5.

side channel leakage

学術雑誌論文

This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/