90008959

open access

Version of Record

Physical Attack Protection Techniques for IC Chip Level Hardware Security

English (英語)

IEEE Transactions On Very Large Scale Integration (VLSI) Systems

30(1)

5-14

Institute of Electrical and Electronics Engineers (IEEE)

2022-01

2022-02-07

Secure hardware systems are threatened by adversarial attempts on integrated circuit (IC) chips in a practical utilization environment. This article provides overviews of physical attacks on cryptographic circuits, associated vulnerabilities in an IC chip, and protection schemes in the vertical unification of systems, circuits, and packaging technologies. The design principles of on-chip monitoring circuits to sense the attackers' attempts are discussed and tested with Si demonstrators. Physical structures are explored for secure IC chips to establish protections against multimodal side-channel attacks. The backside buried metal (BBM) wirings in a Si substrate are unified with its frontside complementary metal-oxide semiconductor (CMOS) circuits to achieve avoidance, detection, and resiliency against electromagnetic and laser attacks.

Si substrate attack

学術雑誌論文

This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/